When: November 9, 2016, 12:30 PM
Location: 3rd Floor Orchard View Room , Discovery Building
Contact: 608-316-4401, email@example.com
Deep Learning in the Enhanced Cloud
Deep Learning has emerged as a singularly critical technology for enabling human-like intelligence in online services such as Azure, Office 365, Bing, Cortana, Skype, and other high-valued scenarios at Microsoft. While Deep Neural Networks (DNNs) have enabled state-of-the-art accuracy in many intelligence tasks, they are notoriously expensive and difficult to deploy in hyperscale datacenters constrained by power, cost, and latency. Furthermore, the escalating (and insatiable) demand for DNNs comes at an inopportune time as ideal silicon scaling (Moore’s Law) comes to a diminishing end.
At Microsoft, we have developed a new cloud architecture that’s enhanced using a post-CPU technology called FPGA (Field Programmable Gate Array). FPGAs can be viewed as programmable silicon and are being deployed into each and every new server in Microsoft’s hyperscale infrastructure. The flexibility of FPGAs combined with a novel Hardware-as-a-Service (HaaS) architecture unlocks the full potential of a completely programmable hardware and software acceleration plane. In this talk, I’ll give a history and overview of the project, discuss the key enabling technologies behind our enhanced cloud, present opportunities to harness this technology for accelerated deep learning, and conclude with directions for future work.
Eric Chung is a Researcher at Microsoft Research. He is broadly interested in computer architecture, machine learning, cloud architectures, distributed systems, reconfigurable computing, FPGAs, and high-level synthesis. Eric is a major contributor to the research, development, and production deployment of the Catapult project at Microsoft, which uses a scalable fabric of interconnected FPGAs to accelerate cloud services. Currently, Eric leads a team within Catapult to develop and deploy deep learning at cloud scale.
Previously, Eric led the CoRAM project at CMU, an architecture that raised the level of abstraction for FPGA programmers. He was also the principal lead on ProtoFlex, a multi-core FPGA-based full-system simulator. Eric received his PhD from Carnegie Mellon University in 2011, and his B.S. from UC Berkeley in 2004.
The weekly SILO seminar series is made possible through the generous support of the 3M Company and its Advanced Technology Group
SILO is a lecture series with speakers from the UW faculty, graduate students or invited researchers that discuss mathematical related topics. The seminars are organized by WID’s Optimization research group.
SILO’s purpose is to provide a forum that helps connect and recruit mathematically-minded graduate students. SILO is a lunch-and-listen format, where speakers present interesting math topics while the audience eats lunch.